Circuit devices often implement data retention latches (also commonly referred to as retention flip-flops) to retain data during a low power state. However, due to their specific operating characteristics, conventional systems for testing (i.e., debugging) the data retention latches typically implement a relatively large number of pins having a custom arrangement and require complex test sequences driven to these pins. Moreover, this type of testing often makes it difficult to test a circuit device in the field as a debugging system suitable to interface with the custom pin interface and the complex test sequences typically are unavailable outside of the manufacturer's facility. Accordingly, an improved technique for testing circuit devices implementing data retention latches would be advantageous.
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